This invention relates to interconnection layers for microelectronic devices, and more particularly to planarization of insulated interconnection layers.
Integrated circuits such as those found in computers and electronic equipment may contain millions of transistors and other circuit elements fabricated on a single crystal silicon chip. To achieve a desired functionality, a complex network of signal paths must be routed to connect the circuit elements distributed on the surface of the chip. Efficient routing of signals across a chip becomes increasingly difficult as integrated circuit complexity grows. To ease this task, interconnection wiring, which not too many years ago was limited to a single level of metal conductors, on today""s devices may contain as many as five (with even more desired) stacked interconnected levels of densely packed conductors. Each individual level of conductors is typically insulated from adjacent levels by an interlevel dielectric (ILD) such as a silicon dioxide film.
Conductors typically are formed by depositing one or more layers of conductive film over an insulated substrate (which usually contains vias, or through holes allowing, the conductive film to contact underlying circuit structure where electrical connections are needed). Portions of the conductive film are selectively etched away using a mask pattern, leaving a pattern of separate conductors with similar thickness and generally rectangular cross-section on the substrate. Usually, after patterning, the conductors are covered with an ILD before additional conducting layers are added.
Ideally, a completed ILD has a planar upper surface. This ideal is not easily achieved and in multilayer conductor schemes, the inherent topography of the underlying conductors is often replicated on the ILD surface. After several poorly planarized layers of ILD with imbedded conductors are formed, problems due to surface topography that adversely affect wiring reliability are likely to occur, e.g., uneven step coverage or via under/overetching.
To overcome such problems, several methods are in common use for ILD planarization. Chemical mechanical planarization (CMP) abrasively polishes the upper surface of the ILD to smooth topography. Another approach is the etchback process, which generally requires depositing a sacrificial spin-on layer which smooths topography (such as photoresist) over the ILD. The sacrificial layer is etched away, preferably with an etchant which etches the ILD material at a similar rate. Done correctly, the etchback reduces high spots on the ILD layer more than it reduces low spots, thus effecting some level of planarization. Both of these methods can be expensive, time-consuming, and generally require a thick initial ILD deposition, since a top portion of the ILD is removed during planarization.
The present invention provides interconnect structures and methods for increased device planarity. A typical interconnection level contains conductors of several different widths. Conductors which will carry a small current during operation may be layed out using a minimum width established in the design rules for a specific fabrication process. Other conductors which must carry larger current or conform to other design requirements (e.g. alignment tolerances) may be layed out with larger widths. Generally, the largest conducting regions, such as power bus lines and bondpads, are formed on the topmost conducting level, where planarization is not a great concern.
It has now been found that certain ILD deposition processes may naturally planarize conductors (i.e. create a planar ILD upper surface over the conductor edge) narrower than a critical width. Given a specific conductor height, desired ILD deposition depth, and desired planarity, the critical width may be determined for such processes, usually by experimentation. The present invention exploits this property on a conducting level where it is desired to construct a variety of conductors, some of which require a width greater than the critical width. It has now been found that a network of integrally-formed conducting segments may be used to form a conductor which improves ILD deposition planarity and provides a large conductive cross-section. This is apparently the first use of a reticulated (i.e. meshlike) conductor structure to improve ILD planarity. Although such a conductor may require more surface area on the substrate (as compared to a non-reticulated conductor of equivalent length and resistivity), such conductors generally populate a small fraction of the overall area on a given level. In at least one embodiment using reticulated conductors, the ILD planarizes during deposition, thus obviating the need for a CMP or etchback step after deposition. In an alternate embodiment. CMP polish time may be reduced dramatically.
In accordance with the present invention, a method is described herein for constructing a planarized dielectric over a patterned conductor and adjacent regions on a semiconductor device. This method comprises depositing a layer of conducting material on a substrate, and removing the layer of conducting material in a circumscribing region, thereby defining a location for and peripheral walls for a conductor. The method further comprises removing the layer of conducting material from one or more regions within the circumscribing region to form internal walls for the conductor (both removing conducting material steps are preferably performed simultaneously). The current-carrying capability for the conductor is thereby divided amongst two or more integrally-formed conducting segments of smaller minimum horizontal dimension than the overall conductor width. The method may further comprise forming an insulating layer over the conductor and the substrate, preferably by a method which selectively planarizes features in order of smallest to largest, based on minimum horizontal dimension (and more preferably by a method of simultaneous chemical vapor deposition and back-sputtering).
An insulating seed layer may be deposited prior to a back-sputtered deposition, as well as a conventional CVD overlayer (i.e. without significant back-sputter) deposited after a back-sputtered deposition. Alternately, a selectively planarizing deposition may be deposited as a spin-coated dielectric. The conducting segments may be formed at a size and/or spacing equivalent to minimum design rules for the semiconductor device. The device may be chemical mechanical polished after deposition, e.g. to further enhance planarity.
A method is described herein for forming a planarized insulated interconnection structure on a semiconductor device. This method comprises depositing a first layer of conducting material on a substrate and removing sections of the first layer in a predetermined pattern to form a plurality of conducting regions. At least one of the conducting regions is formed as a reticulated conductor, comprising a set of conducting segments integrally-formed to provide multiple conducting paths between opposing ends of the conductor. The method further comprises depositing at least one insulating layer over the conducting regions and substrate by a method of simultaneous deposition and back-sputtering (preferably CVD and back-sputtering, preferably using constituent gasses silane, O2, and argon). The method may further comprise chemical mechanical polishing of the insulating layer. The method may further comprise depositing and patterning a second layer of conducting material over the insulating layer.
The present invention further comprises a metallization structure on a semiconductor device, comprising a plurality of first conducting regions formed on a substrate. At least one of the first conducting regions is a non-reticulated conductor, and at least one of the first conducting regions is a reticulated conductor, comprising a set of conducting segments (preferably formed at a size and/or spacing equivalent to minimum design rules for the device) integrally-formed to provide multiple conducting paths between opposing ends of the reticulated conductor. The structure further comprises one or more insulating layers overlying the first conducting regions and the substrate and providing a top surface which is locally (measured within a 10 xcexcm radius) planar to at least 3000 xc3x85. The structure may further comprise a plurality of second conducting regions formed over the insulating layers, at least one of the second conducting regions electrically connected to at least one of the first conducting regions through the insulating layers.